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47 lines
579 B
Verilog
47 lines
579 B
Verilog
module SN74LS73(
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input clk1, //01
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input clrn1, //02
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input k1, //03
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input clk2, //05
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input clrn2, //06
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input j2, //07
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output qn2, //08
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output reg q2, //09
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input k2, //10
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output reg q1, //12
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output qn1, //13
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input j1 //14
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);
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always@(posedge clk1 or negedge clrn1)
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begin
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if (!clrn1)
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begin
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q1 <= 0;
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end
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else
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begin
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q1 <= ~q1 & j1 | q1 & ~k1;
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end
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end
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assign qn1 = ~q1;
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always@(posedge clk2 or negedge clrn2)
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begin
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if (!clrn2)
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begin
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q2 <= 0;
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end
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else
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begin
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q2 <= ~q2 & j2 | q2 & ~k2;
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end
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end
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assign qn2 = ~q2;
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endmodule
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