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58 lines
657 B
Verilog
58 lines
657 B
Verilog
module SN74LS74(
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input clrn1, //01
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input d1, //02
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input clk1, //03
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input prn1, //04
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output reg q1, //05
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output qn1, //06
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output qn2, //08
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output reg q2, //09
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input prn2, //10
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input clk2, //11
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input d2, //12
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input clrn2 //13
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);
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always@(posedge clk1 or negedge clrn1 or negedge prn1)
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begin
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if (!clrn1)
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begin
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q1 <= 0;
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end
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else
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if (!prn1)
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begin
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q1 <= 1;
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end
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else
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begin
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q1 <= d1;
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end
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end
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assign qn1 = ~q1;
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always@(posedge clk2 or negedge clrn2 or negedge prn2)
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begin
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if (!clrn2)
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begin
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q2 <= 0;
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end
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else
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if (!prn2)
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begin
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q2 <= 1;
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end
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else
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begin
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q2 <= d2;
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end
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end
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assign qn2 = ~q2;
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endmodule
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