mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-25 19:45:57 +00:00
179 lines
3.6 KiB
Systemverilog
179 lines
3.6 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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// MENU for MIST board
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// (C) 2016 Sorgelig
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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module MENU(
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input CLOCK_27, // Input clock 27 MHz
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output LED,
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input SPI_SCK,
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output SPI_DO,
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input SPI_DI,
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input SPI_SS3,
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input CONF_DATA0,
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output [12:0] SDRAM_A,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nWE,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nCS,
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output [1:0] SDRAM_BA,
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output SDRAM_CLK,
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output SDRAM_CKE
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);
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assign LED = 1;
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wire clk_x2, clk_pix, clk_ram, locked;
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pll pll(
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.inclk0(CLOCK_27),
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.c0(clk_ram),
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.c1(SDRAM_CLK),
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.c2(clk_x2),
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.c3(clk_pix),
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.locked(locked)
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);
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//______________________________________________________________________________
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//
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// MIST ARM I/O
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//
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wire scandoubler_disable;
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wire ypbpr;
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wire key_pressed;
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wire [7:0] key_code;
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wire key_strobe;
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user_io #(
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.STRLEN(6))
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user_io(
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.clk_sys (clk_x2 ),
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.conf_str("MENU;;"),
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.SPI_CLK (SPI_SCK ),
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.SPI_SS_IO (CONF_DATA0 ),
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.SPI_MISO (SPI_DO ),
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.SPI_MOSI (SPI_DI ),
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.scandoubler_disable (scandoubler_disable),
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.ypbpr (ypbpr )
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);
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sram ram(
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.*,
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.init(~locked),
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.clk(clk_ram),
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.wtbt(3),
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.dout(),
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.din(0),
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.rd(0),
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.ready()
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);
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reg we;
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reg [24:0] addr = 0;
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always @(posedge clk_ram) begin
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integer init = 5000000;
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reg [4:0] cnt = 9;
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if(init) init <= init - 1;
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else begin
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cnt <= cnt + 1'b1;
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we <= &cnt;
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if(cnt == 8) addr <= addr + 1'd1;
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end
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end
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//______________________________________________________________________________
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//
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// Video
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//
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reg [9:0] hc;
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reg [8:0] vc;
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reg [9:0] vvc;
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reg [22:0] rnd_reg;
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wire [5:0] rnd_c = {rnd_reg[0],rnd_reg[1],rnd_reg[2],rnd_reg[2],rnd_reg[2],rnd_reg[2]};
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wire [22:0] rnd;
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lfsr random(rnd);
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always @(negedge clk_pix) begin
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if(hc == 639) begin
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hc <= 0;
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if(vc == 311) begin
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vc <= 0;
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vvc <= vvc + 9'd6;
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end else begin
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vc <= vc + 1'd1;
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end
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end else begin
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hc <= hc + 1'd1;
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end
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rnd_reg <= rnd;
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end
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reg hb, vb;
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reg hs, vs;
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wire blankn = !(hb & vb);
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always @(posedge clk_pix) begin
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if (hc == 310) hb <= 1;
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else if (hc == 420) hb <= 0;
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if (hc == 336) hs <= 1;
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else if (hc == 368) hs <= 0;
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if(vc == 308) vs <= 1;
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else if (vc == 0) vs <= 0;
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if(vc == 306) vb <= 1;
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else if (vc == 2) vb <= 0;
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end
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reg [7:0] cos_out;
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wire [5:0] cos_g = cos_out[7:3]+6'd32;
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cos cos(vvc + {vc, 2'b00}, cos_out);
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wire [5:0] comp_v = (cos_g >= rnd_c) ? cos_g - rnd_c : 6'd0;
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wire [1:0] rotate;
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mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
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.clk_sys ( clk_x2 ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS3 ( SPI_SS3 ),
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.SPI_DI ( SPI_DI ),
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.R ( blankn ? comp_v : 0 ),
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.G ( blankn ? comp_v : 0 ),
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.B ( blankn ? comp_v : 0 ),
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.HSync ( hs ),
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.VSync ( vs ),
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.VGA_R ( VGA_R ),
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.VGA_G ( VGA_G ),
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.VGA_B ( VGA_B ),
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.VGA_VS ( VGA_VS ),
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.VGA_HS ( VGA_HS ),
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.rotate ( 2'b11 ),
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.ce_divider ( 1 ),
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.scandoubler_disable(scandoubler_disable),
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.ypbpr ( ypbpr )
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);
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endmodule
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