mirror of
https://github.com/Gehstock/Mist_FPGA.git
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122 lines
2.8 KiB
VHDL
122 lines
2.8 KiB
VHDL
-- 8K 256x256 graphics by Emard 2015
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-- License=GPL
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-- Modified Grant Searle's text display to show bitmap graphics
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-- Acknowledgement to his great work!
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-- main web site http://searle.hostei.com/grant/
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-- UK101 page at http://searle.hostei.com/grant/uk101FPGA/index.html
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity OraoGraphDisplay8K is
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port (
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dispAddr : out std_LOGIC_VECTOR(12 downto 0);
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dispData : in std_LOGIC_VECTOR(7 downto 0);
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clk : in std_logic;
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video : out std_logic;
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h_sync : out std_logic;
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v_sync : out std_logic;
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sync : out std_logic
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);
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end OraoGraphDisplay8K;
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architecture rtl of OraoGraphDisplay8K is
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signal hSync : std_logic := '1';
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signal vSync : std_logic := '1';
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signal vActive : std_logic := '0';
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signal hActive : std_logic := '0';
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signal pixelClockCount: STD_LOGIC_VECTOR(3 DOWNTO 0);
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signal pixelCount: STD_LOGIC_VECTOR(2 DOWNTO 0);
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signal horizCount: STD_LOGIC_VECTOR(11 DOWNTO 0);
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signal vertLineCount: STD_LOGIC_VECTOR(8 DOWNTO 0);
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signal charHoriz: STD_LOGIC_VECTOR(12 DOWNTO 0);
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signal charBit: STD_LOGIC_VECTOR(3 DOWNTO 0);
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signal charData: std_LOGIC_VECTOR(7 downto 0);
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begin
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sync <= hSync and vSync;
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h_sync <= hSync;
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v_sync <= vSync;
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dispAddr <= charHoriz;
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charData <= dispData;
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PROCESS (clk)
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BEGIN
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-- Orao display 256x256 bitmap 8K
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-- 5 lines vsync
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-- 30 lines to start of display
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-- 313 lines per frame
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-- 64uS per horiz line (3200 clocks)
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-- 4.7us horiz sync (235 clocks)
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if rising_edge(clk) then
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IF horizCount < 3200 THEN
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horizCount <= horizCount + 1;
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-- horizontal position of the screen
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if (horizCount < 780) or (horizCount > 2830) then
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hActive <= '0';
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pixelClockCount <= (others => '0');
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else
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hActive <= '1';
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end if;
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else
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horizCount<= (others => '0');
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pixelCount<= (others => '0');
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if vertLineCount > 312 then
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vertLineCount <= (others => '0');
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else
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if vertLineCount < 38 or vertLineCount > 293 then
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vActive <= '0';
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charHoriz <= (others => '0');
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else
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vActive <= '1';
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end if;
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vertLineCount <=vertLineCount+1;
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end if;
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END IF;
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if horizCount < 235 then
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hSync <= '0';
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else
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hSync <= '1';
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end if;
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if vertLineCount < 5 then
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vSync <= '0';
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else
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vSync <= '1';
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end if;
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if hActive='1' and vActive = '1' then
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if pixelClockCount < 7 then
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pixelClockCount <= pixelClockCount+1;
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else
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video <= charData(conv_integer(pixelCount));
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pixelClockCount <= (others => '0');
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if pixelCount = 7 then
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charHoriz <= charHoriz+1;
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end if;
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pixelCount <= pixelCount+1;
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end if;
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else
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video <= '0';
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end if;
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end if;
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END PROCESS;
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end rtl;
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