mirror of
https://github.com/Gehstock/Mist_FPGA.git
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80 lines
1.6 KiB
Verilog
80 lines
1.6 KiB
Verilog
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module keyboard
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(
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input clk,
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input reset,
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input ps2_kbd_clk,
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input ps2_kbd_data,
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output reg[7:0] joystick
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);
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reg [11:0] shift_reg = 12'hFFF;
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wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
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wire [7:0] kcode = kdata[9:2];
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reg release_btn = 0;
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reg [7:0] code;
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reg input_strobe = 0;
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always @(negedge clk) begin
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reg old_reset = 0;
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old_reset <= reset;
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if(~old_reset & reset)begin
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joystick <= 0;
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end
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if(input_strobe) begin
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case(code)
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'h16: joystick[4] <= ~release_btn; // 1
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'h1E: joystick[5] <= ~release_btn; // 2
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'h26: joystick[6] <= ~release_btn; // 3
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'h25: joystick[7] <= ~release_btn; // 4
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'h75: joystick[3] <= ~release_btn; // arrow up
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'h72: joystick[2] <= ~release_btn; // arrow down
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'h6B: joystick[1] <= ~release_btn; // arrow left
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'h74: joystick[0] <= ~release_btn; // arrow right
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endcase
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end
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end
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always @(posedge clk) begin
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reg [3:0] prev_clk = 0;
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reg old_reset = 0;
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reg action = 0;
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old_reset <= reset;
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input_strobe <= 0;
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if(~old_reset & reset)begin
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prev_clk <= 0;
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shift_reg <= 12'hFFF;
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end else begin
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prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
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if(prev_clk == 1) begin
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if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
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shift_reg <= 12'hFFF;
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if (kcode == 8'he0) ;
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// Extended key code follows
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else if (kcode == 8'hf0)
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// Release code follows
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action <= 1;
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else begin
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// Cancel extended/release flags for next time
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action <= 0;
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release_btn <= action;
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code <= kcode;
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input_strobe <= 1;
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end
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end else begin
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shift_reg <= kdata;
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end
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end
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end
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end
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endmodule
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