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120 lines
4.4 KiB
VHDL
120 lines
4.4 KiB
VHDL
-- Copyright (c) 2015, $ME
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-- All rights reserved.
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--
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-- Redistribution and use in source and synthezised forms, with or without modification, are permitted
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-- provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice, this list of conditions
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-- and the following disclaimer.
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--
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-- 2. Redistributions in synthezised form must reproduce the above copyright notice, this list of conditions
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-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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-- WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- simple interrupt controller
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-- - no retriggering of ints after int acknowledge
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity intController is
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generic (
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numInts : integer := 8
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);
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port (
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clk : in std_logic;
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res_n : in std_logic;
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int_n : out std_logic;
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intPeriph : in std_logic_vector(numInts-1 downto 0);
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intAck : out std_logic_vector(numInts-1 downto 0);
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cpuDIn : in std_logic_vector(7 downto 0);
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m1_n : in std_logic;
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iorq_n : in std_logic;
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rd_n : in std_logic;
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RETI_n : in std_logic
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);
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end intController;
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architecture rtl of intController is
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constant zeroVect : std_logic_vector(numInts-1 downto 0) := (others => '0');
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signal intInternal : std_logic_vector(numInts-1 downto 0);
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signal intMask : std_logic_vector(numInts-1 downto 0);
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signal currentInt : std_logic_vector(numInts-1 downto 0);
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type controllerStates is (idle, intAccepted, waitForRetiEnd, waitForM1, finishInt);
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signal state : controllerStates := idle;
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begin
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intAck <= currentInt when m1_n='0' and iorq_n='0' else (others => '0');
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-- determine int with highest priority
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int_mask : process(intInternal)
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begin
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intMask <= (others => '0');
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for i in 0 to numInts-1 -- 0 is highest prio
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loop
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if intInternal(i)='1' then
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intMask(i) <= '1';
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exit;
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end if;
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end loop;
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end process;
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-- handle ints
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process
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variable intResetMask : std_logic_vector(numInts-1 downto 0);
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begin
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wait until rising_edge(clk);
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if (res_n='0') then
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state <= idle;
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int_n <= '1';
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currentInt <= (others => '0');
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intInternal <= (others => '0');
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else
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intResetMask := (others => '1');
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if (m1_n='1') then
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if intMask /= zeroVect and state=idle then -- new int + update to higher prio until int ack
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int_n <= '0';
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currentInt <= intMask;
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end if;
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if RETI_n='0' and state=intAccepted then
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state <= waitForRetiEnd;
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elsif RETI_n='1' and state=waitForRetiEnd then
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state <= waitForM1;
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elsif state=finishInt then
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currentInt <= (others => '0'); -- restart int cycle
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state <= idle;
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end if;
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else
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if state=waitForM1 then -- allow int after 1 additional m1-cycle
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state <= finishInt;
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end if;
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if iorq_n='0' then -- int ack
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state <= intAccepted;
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int_n <= '1';
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intResetMask := not currentInt; -- reset current int
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end if;
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end if;
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intInternal <= (intInternal and intResetMask) or intPeriph;
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end if;
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end process;
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end;
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