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37 lines
831 B
VHDL
37 lines
831 B
VHDL
-- einfacher blockram
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sram is
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generic(
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AddrWidth : integer := 11;
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DataWidth : integer := 8
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);
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port (
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clk : in std_logic;
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addr : in std_logic_vector(AddrWidth - 1 downto 0);
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din : in std_logic_vector(DataWidth - 1 downto 0);
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dout : out std_logic_vector(DataWidth - 1 downto 0);
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we_n : in std_logic;
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ce_n : in std_logic
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);
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end sram;
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architecture rtl of sram is
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type mem is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
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signal ram: mem(0 to 2 ** AddrWidth - 1) := (others => (others => '0'));
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begin
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process
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begin
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wait until rising_edge(clk);
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if we_n = '0' and ce_n = '0' then
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ram(to_integer(unsigned(addr))) <= din;
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end if;
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dout <= ram(to_integer(unsigned(addr)));
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end process;
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end rtl;
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