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52 lines
1.6 KiB
Systemverilog
52 lines
1.6 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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`default_nettype none
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module IP(input logic clk,
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input logic reset,
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input logic start_instruction,
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input logic next_instruction,
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input logic rollback,
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input logic [3:0] inc,
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input logic wr_en,
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input logic [15:0] wr_val,
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output logic [15:0] val);
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reg [15:0] cur_val;
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reg [15:0] instruction_start_addr;
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assign val = cur_val;
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always_ff @(posedge clk or posedge reset)
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if (reset)
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instruction_start_addr <= 16'b0;
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else if (start_instruction || next_instruction)
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instruction_start_addr <= wr_en ? wr_val : cur_val;
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else if (next_instruction)
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instruction_start_addr <= cur_val;
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always @(posedge clk or posedge reset)
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if (reset)
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cur_val <= 16'b0;
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else if (wr_en)
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cur_val <= wr_val;
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else if (rollback)
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cur_val <= instruction_start_addr;
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else if (start_instruction)
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cur_val <= cur_val + {12'b0, inc};
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endmodule
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