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64 lines
2.0 KiB
Systemverilog
64 lines
2.0 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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`default_nettype none
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module SegmentOverride(input logic clk,
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input logic reset,
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input logic next_instruction,
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input logic flush,
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input logic update,
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input logic force_segment,
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input logic bp_is_base,
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input logic segment_override,
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input logic [1:0] override_in,
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input logic [1:0] microcode_sr_rd_sel,
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output logic [1:0] sr_rd_sel);
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reg [1:0] override;
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reg override_active;
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always_comb begin
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if (force_segment)
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sr_rd_sel = microcode_sr_rd_sel;
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else if (update && segment_override)
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sr_rd_sel = override_in;
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else if (override_active)
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sr_rd_sel = override;
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else if (bp_is_base)
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sr_rd_sel = SS;
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else
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sr_rd_sel = microcode_sr_rd_sel;
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end
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always_ff @(posedge clk or posedge reset) begin
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if (reset) begin
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override_active <= 1'b0;
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override <= 2'b00;
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end else begin
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if (next_instruction || flush) begin
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override_active <= 1'b0;
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override <= 2'b00;
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end
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if (update && segment_override) begin
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override <= override_in;
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override_active <= 1'b1;
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end
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end
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end
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endmodule
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