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19 lines
1.7 KiB
Verilog
19 lines
1.7 KiB
Verilog
/*******************************************************************************************/
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/** **/
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/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** **/
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/** chip design file include list Rev 0.0 07/17/2011 **/
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/** **/
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/*******************************************************************************************/
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`include "defines.v" /* control signal mnemonics */
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`include "control.v" /* processor control */
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`include "datapath.v" /* processor data path */
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`include "alu_log.v" /* alu logic unit */
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`include "alu_math.v" /* alu math unit */
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`include "alu_shft.v" /* alu shifter unit */
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`include "aluamux.v" /* alu a input multiplexer */
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`include "alubmux.v" /* alu b input multiplexer */
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`include "aluout.v" /* alu output multiplexer */
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`include "extint.v" /* processor external interface */
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`include "machine.v" /* processor state machine */
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`include "y80_top.v" /* cpu top level */ |