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144 lines
3.6 KiB
Plaintext
144 lines
3.6 KiB
Plaintext
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An SN76489AN Compatible Implementation in VHDL
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==============================================
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Version: $Date: 2006/06/18 19:28:40 $
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Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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See the file COPYING.
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Integration
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-----------
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The sn76489 design exhibits all interface signals as the original chip. It
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only differs in the audio data output which is provided as an 8 bit signed
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vector instead of an analog output pin.
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generic (
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clock_div_16_g : integer := 1
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-- Set to '1' when operating the design in SN76489 mode. The primary clock
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-- input is divided by 16 in this variant. The data sheet mentions the
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-- SN76494 which contains a divide-by-2 clock input stage. Set the generic
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-- to '0' to enable this mode.
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);
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port (
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clock_i : in std_logic;
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-- Primary clock input
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-- Drive with the target frequency or any integer multiple of it.
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clock_en_i : in std_logic;
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-- Clock enable
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-- A '1' on this input qualifies a valid rising edge on clock_i. A '0'
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-- disables the next rising clock edge, effectivley halting the design
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-- until the next enabled rising clock edge.
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-- Can be used to run the core at lower frequencies than applied on
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-- clock_i.
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res_n_i : in std_logic;
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-- Asynchronous low active reset input.
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-- Sets all sequential elements to a known state.
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ce_n_i : in std_logic;
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-- Chip enable, low active.
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we_n_i : in std_logic;
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-- Write enable, low active.
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ready_o : out std_logic;
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-- Ready indication to microprocessor.
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d_i : in std_logic_vector(0 to 7);
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-- Data input
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-- MSB 0 ... 7 LSB
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aout_o : out signed(0 to 7)
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-- Audio output, signed vector
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-- MSB/SIGN 0 ... 7 LSB
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);
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Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the
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MSB and bit 7 to be the LSB. This has been implemented according to TI's data
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sheet, thus all register/data format figures apply 1:1 for this design.
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Many systems will flip the system data bus bit wise before it is connected to
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this PSG. This is simply achieved with the following VHDL construct:
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signal data_s : std_logic_vector(7 downto 0);
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...
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d_i => data_s,
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...
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d_i and data_s will be assigned from left to right, resulting in the expected
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bit assignment:
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d_i data_s
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0 7
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1 6
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...
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6 1
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7 0
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As this design is fully synchronous, care has to be taken when the design
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replaces an SN76489 in asynchronous mode. No problems are expected when
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interfacing the code to other synchronous components.
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Design Hierarchy
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----------------
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sn76489_top
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+-- sn76489_latch_ctrl
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+-- sn76489_clock_div
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+-- sn76489_tone
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| \-- sn76489_attentuator
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+-- sn76489_tone
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| \-- sn76489_attentuator
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+-- sn76489_tone
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| \-- sn76489_attentuator
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\-- sn76489_noise
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\-- sn76489_attentuator
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Resulting compilation sequence:
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sn76489_comp_pack-p.vhd
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sn76489_top.vhd
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sn76489_latch_ctrl.vhd
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sn76489_latch_ctrl-c.vhd
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sn76489_clock_div.vhd
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sn76489_clock_div-c.vhd
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sn76489_attenuator.vhd
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sn76489_attenuator-c.vhd
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sn76489_tone.vhd
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sn76489_tone-c.vhd
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sn76489_noise.vhd
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sn76489_noise-c.vhd
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sn76489_top-c.vhd
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Skip the files containing VHDL configurations when analyzing the code for
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synthesis.
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References
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----------
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* TI Data sheet SN76489.pdf
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ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
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* John Kortink's article on the SN76489:
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http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
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* Maxim's "SN76489 notes" in
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http://www.smspower.org/maxim/docs/SN76489.txt
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