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85 lines
1.2 KiB
Systemverilog
85 lines
1.2 KiB
Systemverilog
module TTL74LS373 (
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input LE,
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input [8:1] D,
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input OE_n,
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output [8:1] Q
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);
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reg SYNTHESIZED_WIRE_0;
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reg SYNTHESIZED_WIRE_2;
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reg SYNTHESIZED_WIRE_4;
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reg SYNTHESIZED_WIRE_6;
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reg SYNTHESIZED_WIRE_8;
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reg SYNTHESIZED_WIRE_10;
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reg SYNTHESIZED_WIRE_12;
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reg SYNTHESIZED_WIRE_14;
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always@(LE or D[1])
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begin
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if (LE)
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SYNTHESIZED_WIRE_0 <= D[1];
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end
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always@(LE or D[2])
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begin
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if (LE)
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SYNTHESIZED_WIRE_2 <= D[2];
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end
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always@(LE or D[3])
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begin
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if (LE)
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SYNTHESIZED_WIRE_4 <= D[3];
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end
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always@(LE or D[4])
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begin
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if (LE)
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SYNTHESIZED_WIRE_6 <= D[4];
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end
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always@(LE or D[5])
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begin
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if (LE)
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SYNTHESIZED_WIRE_8 <= D[5];
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end
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always@(LE or D[6])
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begin
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if (LE)
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SYNTHESIZED_WIRE_10 <= D[6];
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end
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always@(LE or D[7])
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begin
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if (LE)
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SYNTHESIZED_WIRE_12 <= D[7];
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end
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always@(LE or D[8])
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begin
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if (LE)
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SYNTHESIZED_WIRE_14 <= D[8];
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end
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assign Q[1] = OE_n ? SYNTHESIZED_WIRE_0 : 1'bz;
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assign Q[2] = OE_n ? SYNTHESIZED_WIRE_2 : 1'bz;
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assign Q[3] = OE_n ? SYNTHESIZED_WIRE_4 : 1'bz;
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assign Q[4] = OE_n ? SYNTHESIZED_WIRE_6 : 1'bz;
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assign Q[5] = OE_n ? SYNTHESIZED_WIRE_8 : 1'bz;
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assign Q[6] = OE_n ? SYNTHESIZED_WIRE_10 : 1'bz;
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assign Q[7] = OE_n ? SYNTHESIZED_WIRE_12 : 1'bz;
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assign Q[8] = OE_n ? SYNTHESIZED_WIRE_14 : 1'bz;
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endmodule
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