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73 lines
2.7 KiB
VHDL
73 lines
2.7 KiB
VHDL
--============================================================================
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--
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-- VHDL implementation of the 74LS139 dual 2-to-4 address decoder
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-- Copyright (C) 2018, 2019 Ace
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a
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-- copy of this software and associated documentation files (the "Software"),
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-- to deal in the Software without restriction, including without limitation
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-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
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-- and/or sell copies of the Software, and to permit persons to whom the
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-- Software is furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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-- DEALINGS IN THE SOFTWARE.
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--
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--============================================================================
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--Chip pinout:
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/* _____________
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_| |_
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n_e(0) |_|1 16|_| VCC
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_| |_
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a0(0) |_|2 15|_| n_e(1)
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_| |_
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a1(0) |_|3 14|_| a0(1)
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_| |_
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o0(0) |_|4 13|_| a1(1)
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o0(1) |_|5 12|_| o1(0)
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o0(2) |_|6 11|_| o1(1)
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_| |_
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o0(3) |_|7 10|_| o1(2)
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_| |_
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GND |_|8 9|_| o1(3)
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|_____________|
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*/
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity ls139 is
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port
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(
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a0 : in std_logic_vector(1 downto 0);
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a1 : in std_logic_vector(1 downto 0);
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n_e : in std_logic_vector(1 downto 0);
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o0 : out std_logic_vector(3 downto 0);
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o1 : out std_logic_vector(3 downto 0)
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);
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end ls139;
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architecture arch of ls139 is
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begin
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o0 <= "1110" when (not n_e(0) and not a0(0) and not a1(0))
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else "1101" when (not n_e(0) and a0(0) and not a1(0))
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else "1011" when (not n_e(0) and not a0(0) and a1(0))
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else "0111" when (not n_e(0) and a0(0) and a1(0))
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else "1111";
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o1 <= "1110" when (not n_e(1) and not a0(1) and not a1(1))
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else "1101" when (not n_e(1) and a0(1) and not a1(1))
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else "1011" when (not n_e(1) and not a0(1) and a1(1))
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else "0111" when (not n_e(1) and a0(1) and a1(1))
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else "1111";
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end arch; |