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112 lines
2.0 KiB
Verilog
112 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 21:05:44 04/24/2018
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// Design Name: LS139
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// Module Name: system86/src/ttl/ls139_tb.v
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// Project Name: Namco System86 simulation
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//// Target Device:
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// Tool versions:
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// Description: LS139 - Dual 2-Line To 4-Line Decoder/Demultiplexer - test bench
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//
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// Verilog Test Fixture created by ISE for module: LS139
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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////////////////////////////////////////////////////////////////////////////////
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module LS139_tb;
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// Inputs
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reg Ea;
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reg A0a;
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reg A1a;
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reg Eb;
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reg A0b;
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reg A1b;
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// Outputs
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wire O0a;
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wire O1a;
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wire O2a;
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wire O3a;
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wire O0b;
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wire O1b;
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wire O2b;
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wire O3b;
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// Instantiate the Unit Under Test (UUT)
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LS139 uut (
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.Ea(Ea),
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.A0a(A0a),
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.A1a(A1a),
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.Eb(Eb),
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.A0b(A0b),
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.A1b(A1b),
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.O0a(O0a),
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.O1a(O1a),
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.O2a(O2a),
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.O3a(O3a),
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.O0b(O0b),
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.O1b(O1b),
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.O2b(O2b),
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.O3b(O3b)
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);
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integer e;
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integer i;
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initial begin
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// Initialize Inputs
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Ea = 0;
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A0a = 0;
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A1a = 0;
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Eb = 0;
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A0b = 0;
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A1b = 0;
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// Wait 100 ns for global reset to finish
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#100;
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// Add stimulus here
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$display("A0\tA1\tEa\tEb\tO0a\tO1a\tO2a\tO3a\tO0b\tO1b\tO2b\tO3b");
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for (e = 0; e < 4; e=e+1) begin
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Ea = e[0];
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Eb = e[1];
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for (i = 0; i < 16; i=i+1) begin
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A0a = i[0];
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A1a = i[1];
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A0b = i[0];
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A1b = i[1];
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#4
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$display("%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s",
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i[0] ? "H" : "L",
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i[1] ? "H" : "L",
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Ea ? "H" : "L",
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Eb ? "H" : "L",
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O0a ? "H" : "L",
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O1a ? "H" : "L",
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O2a ? "H" : "L",
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O3a ? "H" : "L",
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O0b ? "H" : "L",
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O1b ? "H" : "L",
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O2b ? "H" : "L",
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O3b ? "H" : "L",);
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end
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end
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$finish;
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end
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endmodule
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