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125 lines
2.1 KiB
Verilog
125 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 20:24:08 04/24/2018
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// Design Name: LS153
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// Module Name: system86/src/ttl/ls153_tb.v
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// Project Name: Namco System86 simulation
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//// Target Device:
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// Tool versions:
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// Description: LS153 - Dual 4-Input Multiplexer - test bench
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//
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// Verilog Test Fixture created by ISE for module: LS153
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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////////////////////////////////////////////////////////////////////////////////
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module LS153_tb;
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// Inputs
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reg S0;
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reg S1;
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reg Ea;
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reg I0a;
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reg I1a;
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reg I2a;
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reg I3a;
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reg Eb;
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reg I0b;
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reg I1b;
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reg I2b;
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reg I3b;
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// Outputs
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wire Za;
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wire Zb;
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// Instantiate the Unit Under Test (UUT)
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LS153 uut (
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.S0(S0),
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.S1(S1),
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.Ea(Ea),
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.I0a(I0a),
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.I1a(I1a),
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.I2a(I2a),
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.I3a(I3a),
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.Eb(Eb),
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.I0b(I0b),
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.I1b(I1b),
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.I2b(I2b),
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.I3b(I3b),
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.Za(Za),
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.Zb(Zb)
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);
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integer e;
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integer s;
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integer i;
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initial begin
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// Initialize Inputs
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S0 = 0;
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S1 = 0;
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Ea = 0;
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I0a = 0;
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I1a = 0;
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I2a = 0;
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I3a = 0;
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Eb = 0;
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I0b = 0;
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I1b = 0;
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I2b = 0;
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I3b = 0;
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// Wait 100 ns for global reset to finish
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#100;
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// Add stimulus here
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$display("S0\tS1\tI0\tI1\tI2\tI3\tEa\tEb\tZa\tZb");
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for (e = 0; e < 4; e=e+1) begin
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Ea = e[0];
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Eb = e[1];
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for (s = 0; s < 4; s=s+1) begin
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S0 = s[0];
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S1 = s[1];
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for (i = 0; i < 16; i=i+1) begin
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I0a = i[0];
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I1a = i[1];
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I2a = i[2];
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I3a = i[3];
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I0b = i[0];
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I1b = i[1];
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I2b = i[2];
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I3b = i[3];
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#4
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$display("%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s",
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S0 ? "H" : "L",
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S1 ? "H" : "L",
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i[0] ? "H" : "L",
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i[1] ? "H" : "L",
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i[2] ? "H" : "L",
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i[3] ? "H" : "L",
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Ea ? "H" : "L",
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Eb ? "H" : "L",
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Za ? "H" : "L",
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Zb ? "H" : "L");
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end
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end
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end
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$finish;
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end
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endmodule
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