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69 lines
2.2 KiB
VHDL
69 lines
2.2 KiB
VHDL
--============================================================================
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--
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-- VHDL implementation of the 74LS174 hex D-flip flop
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-- Copyright (C) 2018, 2019 Ace
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a
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-- copy of this software and associated documentation files (the "Software"),
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-- to deal in the Software without restriction, including without limitation
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-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
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-- and/or sell copies of the Software, and to permit persons to whom the
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-- Software is furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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-- DEALINGS IN THE SOFTWARE.
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--
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--============================================================================
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--Chip pinout:
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/* _____________
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_| |_
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mr |_|1 16|_| VCC
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_| |_
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q(0) |_|2 15|_| q(5)
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_| |_
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d(0) |_|3 14|_| d(5)
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d(1) |_|4 13|_| d(4)
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q(1) |_|5 12|_| q(4)
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d(2) |_|6 11|_| d(3)
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q(2) |_|7 10|_| q(3)
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GND |_|8 9|_| clk
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|_____________|
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*/
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity ls174 is
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port
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(
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d : in std_logic_vector(5 downto 0);
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clk : in std_logic;
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mr : in std_logic;
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q : out std_logic_vector(5 downto 0)
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);
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end ls174;
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architecture arch of ls174 is
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begin
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process(clk, mr) begin
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if(mr = '0') then
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q <= "000000";
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elsif(clk'event and clk = '1') then
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q <= d;
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end if;
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end process;
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end arch; |