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61 lines
2.0 KiB
VHDL
61 lines
2.0 KiB
VHDL
--============================================================================
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--
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-- VHDL implementation of the 74LS20 dual 4-input NAND gate
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-- Copyright (C) 2018, 2019 Ace
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a
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-- copy of this software and associated documentation files (the "Software"),
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-- to deal in the Software without restriction, including without limitation
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-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
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-- and/or sell copies of the Software, and to permit persons to whom the
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-- Software is furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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-- DEALINGS IN THE SOFTWARE.
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--
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--============================================================================
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--Chip pinout:
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/* _____________
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_| |_
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a1 |_|1 14|_| VCC
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_| |_
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b1 |_|2 13|_| d2
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_| |_
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NC |_|3 12|_| c2
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_| |_
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c1 |_|4 11|_| NC
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_| |_
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d1 |_|5 10|_| b2
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_| |_
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y1 |_|6 9|_| a2
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GND |_|7 8|_| y2
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|_____________|
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*/
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity ls20 is
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port
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(
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a1, b1, c1, d1 : in std_logic;
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a2, b2, c2, d2 : in std_logic;
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y1, y2 : out std_logic
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);
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end ls20;
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architecture arch of ls20 is
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begin
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y1 <= not(a1 and b1 and c1 and d1);
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y2 <= not(a2 and b2 and c2 and d2);
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end arch; |