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25 lines
450 B
VHDL
25 lines
450 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity ls245 is
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port
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(
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dir, n_oe : in std_logic;
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a, b : inout std_logic_vector(7 downto 0)
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);
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end ls245;
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architecture arch of ls245 is
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begin
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a <= (others => 'Z');
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b <= (others => 'Z');
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process(dir, n_oe, a, b) begin
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if(n_oe = '0' and dir = '1') then
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a <= (others => 'Z');
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b <= a;
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elsif(n_oe = '0' and dir = '0') then
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b <= (others => 'Z');
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a <= b;
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end if;
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end process;
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end arch; |