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68 lines
2.3 KiB
VHDL
68 lines
2.3 KiB
VHDL
--============================================================================
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--
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-- VHDL implementation of the 74LS283 4-bit full adder with fast carry
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-- Copyright (C) 2018, 2019 Ace
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a
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-- copy of this software and associated documentation files (the "Software"),
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-- to deal in the Software without restriction, including without limitation
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-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
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-- and/or sell copies of the Software, and to permit persons to whom the
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-- Software is furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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-- DEALINGS IN THE SOFTWARE.
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--
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--============================================================================
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--Chip pinout:
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/* _____________
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_| |_
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sum(1) |_|1 16|_| VCC
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_| |_
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b(1) |_|2 15|_| b(2)
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_| |_
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a(1) |_|3 14|_| a(2)
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sum(0) |_|4 13|_| sum(2)
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_| |_
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a(0) |_|5 12|_| a(3)
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b(0) |_|6 11|_| b(3)
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c_in |_|7 10|_| sum(3)
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_| |_
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GND |_|8 9|_| c_out
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|_____________|
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*/
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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entity ls283 is
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port
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(
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a : in std_logic_vector(3 downto 0);
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b : in std_logic_vector(3 downto 0);
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c_in : in std_logic;
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sum : out std_logic_vector(3 downto 0);
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c_out : out std_logic
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);
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end ls283;
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architecture arch of ls283 is
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signal sum_int : std_logic_vector(4 downto 0);
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begin
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sum_int <= ('0' & a) + ('0' & b) + ("0000" & c_in);
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sum <= sum_int(3 downto 0);
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c_out <= sum_int(4);
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end arch; |