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https://github.com/Gehstock/Mist_FPGA.git
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79 lines
2.5 KiB
VHDL
79 lines
2.5 KiB
VHDL
--============================================================================
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--
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-- VHDL implementation of the 74LS393 dual 4-bit binary counter
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-- Copyright (C) 2018, 2019 Ace
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a
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-- copy of this software and associated documentation files (the "Software"),
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-- to deal in the Software without restriction, including without limitation
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-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
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-- and/or sell copies of the Software, and to permit persons to whom the
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-- Software is furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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-- DEALINGS IN THE SOFTWARE.
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--
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--============================================================================
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--Chip pinout:
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/* _____________
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clk1 |_|1 14|_| VCC
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clr1 |_|2 13|_| clk2
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q1(0) |_|3 12|_| clr2
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q1(1) |_|4 11|_| q2(0)
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q1(2) |_|5 10|_| q2(1)
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q1(3) |_|6 9|_| q2(2)
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GND |_|7 8|_| q2(3)
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|_____________|
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*/
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity ls393 is
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port
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(
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clk1, clk2 : in std_logic;
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clr1, clr2 : in std_logic;
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q1, q2 : out std_logic_vector(3 downto 0)
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);
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end ls393;
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architecture arch of ls393 is
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signal count1 : std_logic_vector(3 downto 0);
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signal count2 : std_logic_vector(3 downto 0);
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begin
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process(clk1, clr1) begin
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if(clr1 = '1') then
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count1 <= "0000";
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elsif(clk1'event and clk1 = '0') then
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count1 <= count1 + 1;
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end if;
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end process;
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process(clk2, clr2) begin
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if(clr2 = '1') then
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count2 <= "0000";
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elsif(clk2'event and clk2 = '0') then
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count2 <= count2 + 1;
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end if;
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end process;
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q1 <= count1;
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q2 <= count2;
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end arch; |