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https://github.com/Gehstock/Mist_FPGA.git
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85 lines
2.8 KiB
VHDL
85 lines
2.8 KiB
VHDL
--============================================================================
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--
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-- VHDL implementation of the 74LS669 synchronous 4-bit up/down counter
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-- Copyright (C) 2018, 2019 Ace
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a
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-- copy of this software and associated documentation files (the "Software"),
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-- to deal in the Software without restriction, including without limitation
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-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
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-- and/or sell copies of the Software, and to permit persons to whom the
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-- Software is furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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-- DEALINGS IN THE SOFTWARE.
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--
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--============================================================================
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--Chip pinout:
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/* _____________
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_| |_
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u_d |_|1 16|_| VCC
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_| |_
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clk |_|2 15|_| n_rco
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_| |_
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d_in(0) |_|3 14|_| d_out(0)
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_| |_
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d_in(1) |_|4 13|_| d_out(1)
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_| |_
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d_in(2) |_|5 12|_| d_out(2)
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_| |_
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d_in(3) |_|6 11|_| d_out(3)
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_| |_
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n_en_p |_|7 10|_| n_en_t
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_| |_
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GND |_|8 9|_| load
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|_____________|
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*/
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity ls669 is
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port
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(
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d_in : in std_logic_vector(3 downto 0);
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clk : in std_logic;
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load : in std_logic;
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n_en_p : in std_logic;
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n_en_t : in std_logic;
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u_d : in std_logic;
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d_out : out std_logic_vector(3 downto 0);
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n_rco : out std_logic
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);
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end ls669;
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architecture arch of ls669 is
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signal count: std_logic_vector(3 downto 0);
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begin
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process(clk) begin
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if(clk'event and clk = '1') then
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if(load = '0') then
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count <= d_in;
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elsif(n_en_p = '0' and n_en_t = '0') then
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if(u_d = '1') then
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count <= count + 1;
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else
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count <= count - 1;
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end if;
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end if;
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end if;
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end process;
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d_out <= count;
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n_rco <= (not n_en_t and u_d and count(0) and count(1) and count(2) and count(3))
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nor (not n_en_t and not u_d and not count(0) and not count(1) and not count(2) and not count(3));
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end arch; |