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37 lines
708 B
VHDL
37 lines
708 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity multi74123 is
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Port ( inh_pos : in STD_LOGIC;
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q_neg : out STD_LOGIC;
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clk : in STD_LOGIC);
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end multi74123;
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architecture Behavioral of multi74123 is
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constant pulse_len : integer range 0 to 32767 := 20160;
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signal cnt : integer range 0 to 32767 := 0;
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signal inh_R : std_logic := '0';
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signal inh_R_prev : std_logic := '0';
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if cnt>0 then
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cnt <= cnt - 1;
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end if;
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inh_R_prev <= inh_R;
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inh_R <= inh_pos;
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if inh_R_prev = '0' and inh_R='1' then
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cnt <= pulse_len;
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end if;
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end if;
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end process;
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q_neg <= '0' when (cnt>0) else '1';
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end Behavioral;
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