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59 lines
1.0 KiB
Verilog
59 lines
1.0 KiB
Verilog
module vdp_shift(
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clk40m,
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rst_n,
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pattern,
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color,
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color1,
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color0,
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load,
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text_mode,
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color_1,
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color_0,
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pixel
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);
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input clk40m;
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input rst_n;
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input [ 7 : 0 ] pattern;
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input [ 7 : 0 ] color;
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input [ 3 : 0 ] color1;
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input [ 3 : 0 ] color0;
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input load;
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input text_mode;
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output [ 3 : 0 ] color_1;
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output [ 3 : 0 ] color_0;
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output pixel;
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reg [ 3 : 0 ] color_1;
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reg [ 3 : 0 ] color_0;
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always @( negedge rst_n or posedge clk40m ) begin
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if( !rst_n ) begin
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color_1 <= 0;
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color_0 <= 0;
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end else if( load ) begin
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color_1 <= text_mode ? color1 : color[ 7 : 4 ];
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color_0 <= text_mode ? color0 : color[ 3 : 0 ];
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end
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end
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reg pixel;
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reg [ 6 : 0 ] shift;
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reg [ 1 : 0 ] hrep;
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always @( negedge rst_n or posedge clk40m ) begin
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if( !rst_n ) begin
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pixel <= 0;
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shift <= 0;
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hrep <= 0;
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end else if( load ) begin
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hrep <= 0;
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{ pixel, shift } <= pattern;
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end else if( hrep == 2 ) begin
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hrep <= 0;
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{ pixel, shift } <= { shift[ 6 : 0 ], 1'b0 };
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end else begin
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hrep <= hrep + 1'b1;
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end
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end
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endmodule
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