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https://github.com/Gehstock/Mist_FPGA.git
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85 lines
2.4 KiB
VHDL
85 lines
2.4 KiB
VHDL
-- -----------------------------------------------------------------------
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--
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-- Syntiac's generic VHDL support files.
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--
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-- -----------------------------------------------------------------------
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-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
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-- http://www.syntiac.com/fpga64.html
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--
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-- Modified April 2016 by Dar (darfpga@aol.fr)
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-- http://darfpga.blogspot.fr
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-- Remove address register when writing
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--
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-- -----------------------------------------------------------------------
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--
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-- gen_rwram.vhd
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--
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-- -----------------------------------------------------------------------
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--
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-- generic ram.
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--
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-- -----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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-- -----------------------------------------------------------------------
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entity gen_ram is
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generic (
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dWidth : integer := 8;
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aWidth : integer := 10
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);
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port (
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clk : in std_logic;
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we : in std_logic;
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addr : in std_logic_vector((aWidth-1) downto 0);
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d : in std_logic_vector((dWidth-1) downto 0);
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q : out std_logic_vector((dWidth-1) downto 0)
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);
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end entity;
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-- -----------------------------------------------------------------------
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architecture rtl of gen_ram is
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subtype addressRange is integer range 0 to ((2**aWidth)-1);
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type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
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signal ram: ramDef;
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signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
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signal qReg : std_logic_vector((dWidth-1) downto 0);
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begin
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-- -----------------------------------------------------------------------
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-- Signals to entity interface
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-- -----------------------------------------------------------------------
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-- q <= qReg;
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-- -----------------------------------------------------------------------
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-- Memory write
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-- -----------------------------------------------------------------------
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process(clk)
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begin
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if rising_edge(clk) then
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if we = '1' then
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ram(to_integer(unsigned(addr))) <= d;
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end if;
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end if;
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end process;
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-- -----------------------------------------------------------------------
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-- Memory read
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-- -----------------------------------------------------------------------
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process(clk)
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begin
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if rising_edge(clk) then
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-- qReg <= ram(to_integer(unsigned(rAddrReg)));
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-- rAddrReg <= addr;
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---- qReg <= ram(to_integer(unsigned(addr)));
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q <= ram(to_integer(unsigned(addr)));
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end if;
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end process;
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--q <= ram(to_integer(unsigned(addr)));
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end architecture;
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