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13 lines
772 B
Plaintext
13 lines
772 B
Plaintext
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) mist.vhd]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) user_io.v]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) data_io.v]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mist_video.v]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.sv]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) cofi.sv]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dac.vhd]
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