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146 lines
4.6 KiB
VHDL
146 lines
4.6 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's SN76489AN.
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--
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-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
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--
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-- Latch Control Unit
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity sn76489_latch_ctrl is
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port (
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clock_i : in std_logic;
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clk_en_i : in boolean;
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res_n_i : in std_logic;
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ce_n_i : in std_logic;
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we_n_i : in std_logic;
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d_i : in std_logic_vector(0 to 7);
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ready_o : out std_logic;
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tone1_we_o : out boolean;
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tone2_we_o : out boolean;
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tone3_we_o : out boolean;
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noise_we_o : out boolean;
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r2_o : out std_logic
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);
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end sn76489_latch_ctrl;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of sn76489_latch_ctrl is
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signal reg_q : std_logic_vector(0 to 2);
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signal we_q : boolean;
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signal ready_q : std_logic;
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signal we_n_d : std_logic;
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begin
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-----------------------------------------------------------------------------
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-- Process seq
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--
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-- Purpose:
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-- Implements the sequential elements.
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--
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seq: process (clock_i, res_n_i)
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begin
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if res_n_i = '0' then
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reg_q <= (others => '0');
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we_q <= false;
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ready_q <= '0';
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elsif clock_i'event and clock_i = '1' then
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if clk_en_i then
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we_n_d <= we_n_i;
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elsif we_n_i = '1' then
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we_n_d <= '1';
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end if;
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-- READY Flag Output ----------------------------------------------------
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if ready_q = '0' and we_q then
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if clk_en_i then
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-- assert READY when write access happened
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ready_q <= '1';
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end if;
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elsif ce_n_i = '1' then
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-- deassert READY when access has finished
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ready_q <= '0';
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end if;
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-- Register Selection ---------------------------------------------------
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if clk_en_i then
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if ce_n_i = '0' and we_n_d = '1' and we_n_i = '0' then
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if d_i(0) = '1' then
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reg_q <= d_i(1 to 3);
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end if;
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we_q <= true;
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else
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we_q <= false;
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end if;
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end if;
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end if;
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end process seq;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output mapping
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-----------------------------------------------------------------------------
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tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
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tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
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tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
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noise_we_o <= reg_q(0 to 1) = "11" and we_q;
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r2_o <= reg_q(2);
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ready_o <= ready_q
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when ce_n_i = '0' else
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'1';
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end rtl;
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