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https://github.com/Gehstock/Mist_FPGA.git
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391 lines
12 KiB
VHDL
391 lines
12 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- i8244 Video Display Controller
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--
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-- $Id: i8244_core.vhd,v 1.17 2007/02/05 22:08:59 arnim Exp $
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--
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-- i8244 Core
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2007, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity i8244_core is
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generic (
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is_pal_g : integer := 1
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);
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port (
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-- System Interface -------------------------------------------------------
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clk_i : in std_logic;
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clk_en_i : in std_logic;
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res_n_i : in std_logic;
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-- ROM Interface ----------------------------------------------------------
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rom_addr_o : out std_logic_vector(8 downto 0);
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rom_en_o : out std_logic;
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rom_data_i : in std_logic_vector(7 downto 0);
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-- I8244 Pads Interface ---------------------------------------------------
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intr_n_o : out std_logic;
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stb_i : in std_logic;
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bg_o : out std_logic;
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hsync_o : out std_logic;
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vsync_o : out std_logic;
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ms_i : in std_logic;
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hbl_o : out std_logic;
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vbl_i : in std_logic;
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vbl_o : out std_logic;
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cx_i : in std_logic;
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l_o : out std_logic;
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cs_n_i : in std_logic;
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wr_n_i : in std_logic;
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rd_n_i : in std_logic;
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din_i : in std_logic_vector(7 downto 0);
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dout_o : out std_logic_vector(7 downto 0);
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dout_en_o : out std_logic;
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r_o : out std_logic;
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g_o : out std_logic;
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b_o : out std_logic;
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ale_i : in std_logic;
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snd_o : out std_logic;
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snd_vec_o : out std_logic_vector(3 downto 0)
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);
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end i8244_core;
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use work.i8244_pack.all;
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--
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use work.i8244_grid_pack.grid_cfg_t;
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--
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use work.i8244_major_pack.major_objs_t;
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use work.i8244_major_pack.major_quad_objs_t;
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use work.i8244_major_pack.rom_addr_t;
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use work.i8244_major_pack.rom_data_t;
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--
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use work.i8244_minor_pack.minor_objs_t;
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use work.i8244_minor_pack.minor_patterns_t;
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use work.i8244_minor_pack.minor_obj_range_t;
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--
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use work.i8244_sound_pack.cpu2snd_t;
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use work.i8244_comp_pack.i8244_sync_gen;
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use work.i8244_comp_pack.i8244_grid;
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use work.i8244_comp_pack.i8244_major;
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use work.i8244_comp_pack.i8244_minor;
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use work.i8244_comp_pack.i8244_cpuio;
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use work.i8244_comp_pack.i8244_col_mux;
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use work.i8244_comp_pack.i8244_sound;
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architecture struct of i8244_core is
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-- active reset level
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constant res_level_c : std_logic := '0';
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-- global signals
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signal clk_en_s : boolean;
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signal res_s : boolean;
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-- sync generator signals
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signal clk_rise_en_s,
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clk_fall_en_s : boolean;
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signal hpos_s,
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vpos_s : pos_t;
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signal hbl_s,
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vbl_s : std_logic;
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signal hor_int_s : std_logic;
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-- grid display system signals
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signal grid_cfg_s : grid_cfg_t;
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signal grid_hpix_s,
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grid_vpix_s,
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grid_dpix_s : std_logic;
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-- major display system signals
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signal major_objs_s : major_objs_t;
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signal major_quad_objs_s : major_quad_objs_t;
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signal major_pix_s : std_logic;
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signal major_attr_s : col_attr_t;
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signal major_coll_s : boolean;
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-- minor display system signals
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signal minor_objs_s : minor_objs_t;
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signal minor_patterns_s : minor_patterns_t;
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signal minor_pix_s : std_logic_vector(minor_obj_range_t);
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-- CPU I/O module signals
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signal en_disp_s : std_logic;
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signal grid_bg_col_s : std_logic_vector(6 downto 0);
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-- color mux module signals
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signal minor_cols_s : col_attrs_t(minor_obj_range_t);
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-- enabled pixel signals
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signal grid_hpix_en_s,
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grid_vpix_en_s,
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grid_dpix_en_s,
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major_pix_en_s : std_logic;
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signal minor_pix_en_s : std_logic_vector(minor_obj_range_t);
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-- sound module signals
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signal snd_int_s : boolean;
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signal cpu2snd_s : cpu2snd_t;
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begin
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res_s <= res_n_i = res_level_c;
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clk_en_s <= clk_en_i = '1';
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-----------------------------------------------------------------------------
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-- Sync generator
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-----------------------------------------------------------------------------
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sync_gen_b : i8244_sync_gen
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generic map (
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is_pal_g => is_pal_g
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)
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port map (
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clk_i => clk_i,
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clk_en_i => clk_en_s,
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clk_rise_en_o => clk_rise_en_s,
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clk_fall_en_o => clk_fall_en_s,
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res_i => res_s,
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ms_i => ms_i,
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vbl_i => vbl_i,
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hbl_o => hbl_s,
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hsync_o => hsync_o,
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vsync_o => vsync_o,
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bg_o => bg_o,
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vbl_o => vbl_s,
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hpos_o => hpos_s,
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vpos_o => vpos_s,
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hor_int_o => hor_int_s
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);
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--
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vbl_o <= vbl_s;
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hbl_o <= hbl_s;
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-----------------------------------------------------------------------------
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-- Grid display system
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-----------------------------------------------------------------------------
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grid_b : i8244_grid
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port map (
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clk_i => clk_i,
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clk_en_i => clk_fall_en_s,
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res_i => res_s,
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hpos_i => hpos_s,
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vpos_i => vpos_s,
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hbl_i => hbl_s,
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vbl_i => vbl_s,
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grid_cfg_i => grid_cfg_s,
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grid_hpix_o => grid_hpix_s,
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grid_vpix_o => grid_vpix_s,
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grid_dpix_o => grid_dpix_s
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);
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-----------------------------------------------------------------------------
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-- Major display system
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-----------------------------------------------------------------------------
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major_b : i8244_major
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port map (
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clk_i => clk_i,
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clk_fall_en_i => clk_fall_en_s,
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res_i => res_s,
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hpos_i => hpos_s,
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vpos_i => vpos_s,
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major_objs_i => major_objs_s,
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major_quad_objs_i => major_quad_objs_s,
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rom_addr_o => rom_addr_o,
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rom_en_o => rom_en_o,
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rom_data_i => rom_data_i,
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major_pix_o => major_pix_s,
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major_attr_o => major_attr_s,
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major_coll_o => major_coll_s
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);
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-----------------------------------------------------------------------------
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-- Minor display system
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-----------------------------------------------------------------------------
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minor_b : i8244_minor
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port map (
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clk_i => clk_i,
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clk_rise_en_i => clk_rise_en_s,
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clk_fall_en_i => clk_fall_en_s,
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res_i => res_s,
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hpos_i => hpos_s,
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vpos_i => vpos_s,
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hbl_i => hbl_s,
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vbl_i => vbl_s,
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minor_objs_i => minor_objs_s,
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minor_patterns_i => minor_patterns_s,
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minor_pix_o => minor_pix_s
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);
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-----------------------------------------------------------------------------
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-- Process disp_en
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--
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-- Purpose:
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-- Masks the pixel signals when display is disabled
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--
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disp_en: process (en_disp_s,
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grid_cfg_s,
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grid_hpix_s, grid_vpix_s, grid_dpix_s,
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major_pix_s,
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minor_pix_s)
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begin
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-- enable major an minor pix channels
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if en_disp_s = '1' then
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major_pix_en_s <= major_pix_s;
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minor_pix_en_s <= minor_pix_s;
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else
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major_pix_en_s <= '0';
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minor_pix_en_s <= (others => '0');
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end if;
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-- enable horizontal and vertical grid channels
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if grid_cfg_s.enable = '1' then
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grid_hpix_en_s <= grid_hpix_s;
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grid_vpix_en_s <= grid_vpix_s;
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else
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grid_hpix_en_s <= '0';
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grid_vpix_en_s <= '0';
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end if;
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-- enable dot grid channel
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if grid_cfg_s.dot_en = '1' then
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grid_dpix_en_s <= grid_dpix_s;
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else
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grid_dpix_en_s <= '0';
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end if;
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end process disp_en;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- CPU I/O module
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-----------------------------------------------------------------------------
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cpuio_b : i8244_cpuio
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port map (
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clk_i => clk_i,
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clk_rise_en_i => clk_rise_en_s,
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clk_fall_en_i => clk_fall_en_s,
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res_i => res_s,
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hpos_i => hpos_s,
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vpos_i => vpos_s,
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vbl_i => vbl_s,
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hor_int_i => hor_int_s,
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stb_i => stb_i,
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ale_i => ale_i,
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din_i => din_i,
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dout_o => dout_o,
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dout_en_o => dout_en_o,
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cs_n_i => cs_n_i,
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rd_n_i => rd_n_i,
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wr_n_i => wr_n_i,
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intr_n_o => intr_n_o,
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en_disp_o => en_disp_s,
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grid_bg_col_o => grid_bg_col_s,
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cx_i => cx_i,
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grid_hpix_i => grid_hpix_en_s,
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grid_vpix_i => grid_vpix_en_s,
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grid_dpix_i => grid_dpix_en_s,
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major_pix_i => major_pix_en_s,
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minor_pix_i => minor_pix_en_s,
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major_coll_i => major_coll_s,
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grid_cfg_o => grid_cfg_s,
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major_objs_o => major_objs_s,
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major_quad_objs_o => major_quad_objs_s,
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minor_objs_o => minor_objs_s,
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minor_patterns_o => minor_patterns_s,
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cpu2snd_o => cpu2snd_s,
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snd_int_i => snd_int_s
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);
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-----------------------------------------------------------------------------
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-- Color mux module
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-----------------------------------------------------------------------------
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minor_cols: for obj in minor_obj_range_t generate
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minor_cols_s(obj) <= minor_objs_s(obj).col;
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end generate;
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--
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col_mux_b : i8244_col_mux
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port map (
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clk_i => clk_i,
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clk_en_i => clk_en_s,
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res_i => res_s,
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hbl_i => hbl_s,
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vbl_i => vbl_s,
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grid_bg_col_i => grid_bg_col_s,
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grid_hpix_i => grid_hpix_en_s,
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grid_vpix_i => grid_vpix_en_s,
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grid_dpix_i => grid_dpix_en_s,
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major_pix_i => major_pix_en_s,
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major_attr_i => major_attr_s,
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minor_pix_i => minor_pix_en_s,
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minor_attrs_i => minor_cols_s,
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r_o => r_o,
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g_o => g_o,
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b_o => b_o,
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l_o => l_o
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);
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-----------------------------------------------------------------------------
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-- Sound module
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-----------------------------------------------------------------------------
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sound_b : i8244_sound
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port map (
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clk_i => clk_i,
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clk_en_i => clk_fall_en_s,
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res_i => res_s,
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hbl_i => hbl_s,
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cpu2snd_i => cpu2snd_s,
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snd_int_o => snd_int_s,
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snd_o => snd_o,
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snd_vec_o => snd_vec_o
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);
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end struct;
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