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16 lines
266 B
Systemverilog
16 lines
266 B
Systemverilog
module TTL74LS245 (
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input OE,
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input DIR,
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input [7:0] Ain,
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output [7:0]Aout,
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input [7:0] Bin,
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output [7:0]Bout
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);
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always @ (OE, DIR, Ain,Bin) begin
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if (OE== 1'b0 & DIR == 1'b1)
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Bout = Ain;
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else if (OE== 1'b0 & DIR == 1'b0)
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Aout = Bin;
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end
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endmodule
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