mirror of
https://github.com/Gehstock/Mist_FPGA.git
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109 lines
2.5 KiB
Verilog
109 lines
2.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 16:27:35 02/19/2008
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// Design Name:
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// Module Name: vga
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module vga(
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input CLK_50MHZ,
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input [1:0] color,
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input RD_n,
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input WR_n,
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output [1:0] VGA_RED,
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output [1:0] VGA_GREEN,
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output [1:0] VGA_BLUE,
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output VGA_HSYNC,
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output VGA_VSYNC,
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output VGA_VBLANK,
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output [11:0] VGA_ADDR,
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input [7:0] VGA_DATA,
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output BUS_REQ,
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input BUS_ACK
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);
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reg [9:0] x = 0;
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reg [9:0] y = 0;
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reg [1:0] counter = 0;
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wire display;
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wire [9:0] gx, gy; //(0,0)-(639,399)
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always @(posedge CLK_50MHZ) begin
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counter <= counter + 1;
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end
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assign gx = x - 144; // (96+48) sync pulse + back porch
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assign gy = y - 71; // (2+29+40)
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always @(posedge counter[0]) begin
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if ( x < 800 )
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begin
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x <= x + 1;
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end else begin
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x <= 0;
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if ( y < 521 )
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y <= y + 1;
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else
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y <= 0;
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end
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end
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// CGROM
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wire [7:0] cgrom_data;
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wire [11:0] cgrom_addr;
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cg_rom cg_rom(
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.address(cgrom_addr),
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.clock(CLK_50MHZ),
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.q(cgrom_data),
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.clken(1'b1)
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);
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wire [1:0] R, G, B;
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Color_Card Color_Card(
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.CLK(CLK_50MHZ),
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.CSX_n(),
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.WR_n(WR_n),
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.CSD_n(),
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.Sync(),
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.RD_n(RD_n),
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.Video(video),
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.Din(VGA_DATA),
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.Dout(),
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.Addr(VGA_ADDR[11:0]),
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.CSDo(),
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.Synco_n(),
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.R(R),
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.G(G),
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.B(B)
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);
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wire [5:0] cx, cy; //(0,0)-(79,24)
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assign cx = gx >> 4;
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assign cy = gy >> 4;
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assign VGA_ADDR = (cy * 40) + cx;
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assign cgrom_addr = {VGA_DATA, gy[3:1]};
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wire video = display & (y[0] & 1) ? cgrom_data[7-(((gx+15)>>1) & 7)] : 0;
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// assign BUS_REQ = ( (96+48-8) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400));
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assign BUS_REQ = ( (96+48-16) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400));
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assign display =( (96+48) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400));
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assign VGA_RED = color[1] ? R : color[0] ? 2'b00 : {video,video};
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assign VGA_GREEN = color[1] ? G : {video,video};
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assign VGA_BLUE = color[1] ? B : color[0] ? 2'b00 : {video,video};
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assign VGA_HSYNC = x < 96 ? 0 : 1;
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assign VGA_VSYNC = y < 2 ? 0 : 1;
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assign VGA_VBLANK = (x == 639 & y == 499) ? 1 : 0;
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endmodule
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