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122 lines
3.7 KiB
VHDL
122 lines
3.7 KiB
VHDL
-- Collision detection logic for for Kee Games Sprint 2
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-- This is called the "Car/Playfield Comparator" in the manual and works by comparing the
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-- video signals representing player and computer cars, track boundaries and oil slicks generating
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-- collision signals when multiple objects appear at the same time (location) in the video.
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-- Car 1 and Car 2 are human players, Car 3 and Car 4 are computer controlled.
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--
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-- NOTE: There is an error in the original schematic, F8 pin 5 should go to CAR1 (not inverted) and
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-- F8 pin 9 to CAR2 (not inverted) while the schematic shows them connecting to the inverted signals
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--
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-- Tests for the following conditions:
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-- Car 1 equals Car 2
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-- Car 1 equals Car 3 or 4
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-- Car 2 equals Car 3 or 4
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-- Car 1 equals Black Playfield (Oil slick)
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-- Car 2 equals Black Playfield (Oil slick)
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-- Car 1 equals White Playfield (Track boundary)
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-- Car 2 equals White Playfield (Track boundary)
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--
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-- (c) 2017 James Sweet
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--
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-- This is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU General
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-- Public License as published by the Free Software
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-- Foundation, either version 3 of the License, or (at your
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-- option) any later version.
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--
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-- This is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the
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-- implied warranty of MERCHANTABILITY or FITNESS FOR A
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-- PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity collision_detect is
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port(
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Clk6 : in std_logic;
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Car1 : in std_logic;
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Car1_n : in std_logic;
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Car2 : in std_logic;
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Car2_n : in std_logic;
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Car3_4_n : in std_logic;
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WhitePF_n : in std_logic;
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BlackPF_n : in std_logic;
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CollRst1_n : in std_logic;
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CollRst2_n : in std_logic;
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Collisions1 : out std_logic_vector(1 downto 0);
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Collisions2 : out std_logic_vector(1 downto 0)
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);
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end collision_detect;
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architecture rtl of collision_detect is
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signal Col_latch_Q : std_logic_vector(4 downto 1) := (others => '0');
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signal S1_n : std_logic_vector(4 downto 1);
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signal S2_n : std_logic_vector(4 downto 1);
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signal R_n : std_logic_vector(4 downto 1);
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begin
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-- Tristate buffers at E5 and E6 route collision signals to data bus 7-6
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Collisions1 <= Col_latch_Q(2 downto 1);
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Collisions2 <= Col_latch_Q(4 downto 3);
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-- 74LS279 quad SR latch at H6, all inputs are active low
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-- These should probably be written as synchronous latches
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H6: process(Clk6, S1_n, S2_n, R_n, Col_latch_Q)
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begin
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if rising_edge(Clk6) then
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-- Units 1 and 3 each have an extra Set element
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-- Ordered from top to bottom as drawn in the schematic
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if R_n(1) = '0' then
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Col_latch_Q(1) <= '0';
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elsif (S1_n(1) and S2_n(1)) = '0' then
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Col_latch_Q(1) <= '1';
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else
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Col_latch_Q(1) <= Col_latch_Q(1);
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end if;
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if R_n(2) = '0' then
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Col_latch_Q(2) <= '0';
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elsif S1_n(2) = '0' then
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Col_latch_Q(2) <= '1';
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else
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Col_latch_Q(2) <= Col_latch_Q(2);
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end if;
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if R_n(4) = '0' then
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Col_latch_Q(4) <= '0';
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elsif S1_n(4) = '0' then
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Col_latch_Q(4) <= '1';
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else
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Col_latch_Q(4) <= Col_latch_Q(4);
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end if;
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if R_n(3) = '0' then
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Col_latch_Q(3) <= '0';
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elsif (S1_n(3) and S2_n(3)) = '0' then
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Col_latch_Q(3) <= '1';
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else
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Col_latch_Q(3) <= Col_latch_Q(3);
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end if;
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end if;
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end process;
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-- Glue logic
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S2_n(1) <= BlackPF_n or Car1_n;
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S1_n(1) <= Car1 nand (Car2_n nand Car3_4_n);
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R_n(1) <= CollRst1_n;
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R_n(2) <= CollRst1_n;
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S1_n(2) <= Car1_n or WhitePF_n;
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R_n(4) <= CollRst2_n;
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S1_n(4) <= Car2_n or WhitePF_n;
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S2_n(3) <= BlackPF_n or Car2_n;
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S1_n(3) <= Car2 nand (Car1_n nand Car3_4_n);
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R_n(3) <= CollRst2_n;
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end rtl; |