mirror of
https://github.com/Gehstock/Mist_FPGA.git
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58 lines
1.5 KiB
Verilog
58 lines
1.5 KiB
Verilog
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module spram #(parameter DATAWIDTH=8, ADDRWIDTH=8, NUMWORDS=1<<ADDRWIDTH, MEM_INIT_FILE="") (
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address,
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clock,
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data,
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wren,
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q);
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input [ADDRWIDTH-1:0] address;
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input clock;
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input [DATAWIDTH-1:0] data;
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input wren;
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output [DATAWIDTH-1:0] q;
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_a (q),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone III",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = NUMWORDS,
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altsyncram_component.operation_mode = "SINGLE_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = ADDRWIDTH,
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altsyncram_component.width_a = DATAWIDTH,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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