mirror of
https://github.com/Gehstock/Mist_FPGA.git
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88 lines
2.5 KiB
Systemverilog
88 lines
2.5 KiB
Systemverilog
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module video(
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input clk,//vga
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input clk7p16,//rgb
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output ce_pxl,
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input white,
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// from lcd ctrl registers
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input ce,
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input [7:0] lcd_xsize,
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input [7:0] lcd_ysize,
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input [7:0] lcd_xscroll,
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input [7:0] lcd_yscroll,
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output lcd_pulse,
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// to/from vram
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output [12:0] addr,
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input [7:0] data,
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// to vga interface
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output hsync,
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output vsync,
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output hblank,
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output vblank,
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output reg [7:0] red,
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output reg [7:0] green,
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output reg [7:0] blue
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);
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reg [9:0] hcount;
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reg [9:0] vcount;
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assign lcd_pulse = ce_pxl;
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// VGA industry standard 640x480@60 800 525 31.5 - - 25.2 16 96 48 10 2 33 MHi modelines table
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// visible area | front porch <sync pulse> back porch
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// 640 | 32 < 48 > 112
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assign hsync = ~((hcount >= 672) && (hcount < 720));
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assign vsync = ~((vcount >= 481) && (vcount < 484));
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assign hblank = hcount > 639;
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assign vblank = vcount > 479;
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// convert vga coordinates to lcd coordinates (with borders)
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wire [8:0] vgax = hcount < 640 ? hcount[9:1] : 9'd0; // 0 - 319
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wire [8:0] vgay = vcount < 480 ? vcount[9:1] : 9'd0; // 0 - 239
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wire [7:0] lcdx = vgax >= 80 && vgax < 240 ? vgax - 8'd80 : 8'd0; // 0-79(80)|80-239(160)|240-319(80)
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wire [7:0] lcdy = vgay >= 40 && vgay < 200 ? vgay - 8'd40 : 8'd0; // 0-39(40)|40-199(160)|200-239(40)
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// calcul vram address (TODO include xsize, ysize, xscroll[1:0] in calculation)
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//assign addr = lcd_yscroll * 8'h30 + lcd_xscroll[7:2] + lcdy * 8'h30 + lcdx[7:2];
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assign addr = lcdy * 8'h30 + lcdx[7:2];
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assign ce_pxl = hcount[0] == 1;
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// assign colors
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wire [2:0] index = { lcdx[1:0], 1'b0 };
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always @(posedge clk)
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if (ce && lcdx != 0 && lcdy != 0) begin
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if (ce_pxl) begin
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case ({white,data[index+:2]})
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3'b000: { red, green, blue } <= 24'h87BA6B;//lightest colour
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3'b001: { red, green, blue } <= 24'h6BA378;//1/3rd darkness
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3'b010: { red, green, blue } <= 24'h386B82;//2/3rd darkness
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3'b011: { red, green, blue } <= 24'h384052;//dark as possible
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3'b100: { red, green, blue } <= 24'hFFFFFF;//white
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3'b101: { red, green, blue } <= 24'hC0C0C0;//light gray
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3'b110: { red, green, blue } <= 24'h808080;//gray
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3'b111: { red, green, blue } <= 24'h000000;//black
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endcase
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end
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end
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else
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{ red, green, blue } <= 24'h0;
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always @(posedge clk) begin
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hcount <= hcount + 10'd1;
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if (hcount == 10'd799) hcount <= 0;
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end
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always @(posedge clk)
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if (hcount == 10'd799)
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vcount <= vcount + 10'd1;
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else if (vcount == 10'd509)
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vcount <= 0;
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endmodule
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