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32 lines
626 B
Verilog
32 lines
626 B
Verilog
module SN74LS138 (
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input a, //01
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input b, //02
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input c, //03
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input g2an, //04
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input g2bn, //05
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input g1, //06
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output y7n, //07
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output y6n, //09
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output y5n, //10
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output y4n, //11
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output y3n, //12
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output y2n, //13
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output y1n, //14
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output y0n //15
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);
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wire en;
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assign en = ~(~g1 | g2bn | g2an);
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assign y0n = ~(~a & ~b & ~c & en);
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assign y1n = ~(a & ~b & ~c & en);
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assign y2n = ~(~a & b & ~c & en);
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assign y3n = ~(a & b & ~c & en);
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assign y4n = ~(~a & ~b & c & en);
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assign y5n = ~(~b & c & a & en);
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assign y6n = ~(~a & c & b & en);
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assign y7n = ~(en & b & a & c);
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endmodule
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