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101 lines
3.2 KiB
VHDL
101 lines
3.2 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- The T48 Bus Connector.
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-- Multiplexes all drivers of the T48 bus.
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--
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-- $Id: bus_mux.vhd 295 2009-04-01 19:32:48Z arniml $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t48_pack.word_t;
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entity t48_bus_mux is
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port (
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alu_data_i : in word_t;
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bus_data_i : in word_t;
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dec_data_i : in word_t;
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dm_data_i : in word_t;
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pm_data_i : in word_t;
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p1_data_i : in word_t;
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p2_data_i : in word_t;
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psw_data_i : in word_t;
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tim_data_i : in word_t;
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data_o : out word_t
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);
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end t48_bus_mux;
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use work.t48_pack.bus_idle_level_c;
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architecture rtl of t48_bus_mux is
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begin
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or_tree: if bus_idle_level_c = '0' generate
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data_o <= alu_data_i or
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bus_data_i or
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dec_data_i or
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dm_data_i or
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pm_data_i or
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p1_data_i or
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p2_data_i or
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psw_data_i or
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tim_data_i;
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end generate;
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and_tree: if bus_idle_level_c = '1' generate
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data_o <= alu_data_i and
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bus_data_i and
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dec_data_i and
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dm_data_i and
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pm_data_i and
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p1_data_i and
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p2_data_i and
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psw_data_i and
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tim_data_i;
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end generate;
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end rtl;
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