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Gehstock.Mist_FPGA/common/Sound/jtopl/jt26.qip
2022-06-28 01:40:35 +02:00

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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_csr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_div.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_lfo.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pm.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_ctrl.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_final.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_pure.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_step.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_exprom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_logsin.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_op.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_inc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_sum.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_rhy.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg_ch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh_rst.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_single_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_timers.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_noise.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_slot_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl.v]