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48 lines
1.1 KiB
Verilog
48 lines
1.1 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 10-6-2020
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*/
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module jtopl_div(
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input rst,
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input clk,
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input cen,
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output reg cenop // clock enable at operator rate
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);
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parameter OPL_TYPE=1;
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localparam W = 2; // OPL_TYPE==2 ? 1 : 2;
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reg [W-1:0] cnt;
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`ifdef SIMULATION
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initial cnt={W{1'b0}};
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`endif
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always @(posedge clk) if(cen) begin
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cnt <= cnt+1'd1;
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end
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always @(posedge clk) begin
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cenop <= cen && (&cnt);
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end
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endmodule
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