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52 lines
1.7 KiB
Verilog
52 lines
1.7 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 13-6-2020
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*/
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// Original hardware uses an adder to do the multiplication
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// but I think it will take less resources of the FPGA to
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// use a real multiplier instead
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module jtopl_pg_sum (
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input [ 3:0] mul,
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input [18:0] phase_in,
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input pg_rst,
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input [16:0] phinc_pure,
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output reg [18:0] phase_out,
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output reg [ 9:0] phase_op
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);
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reg [21:0] phinc_mul;
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reg [ 4:0] factor[0:15];
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always @(*) begin
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phinc_mul = { 5'b0, phinc_pure} * factor[mul];
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phase_out = pg_rst ? 'd0 : (phase_in + phinc_mul[19:1]);
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phase_op = phase_out[18:9];
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end
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initial begin
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factor[ 0] = 5'd01; factor[ 1] = 5'd02; factor[ 2] = 5'd04; factor[ 3] = 5'd06;
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factor[ 4] = 5'd08; factor[ 5] = 5'd10; factor[ 6] = 5'd12; factor[ 7] = 5'd14;
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factor[ 8] = 5'd16; factor[ 9] = 5'd18; factor[10] = 5'd20; factor[11] = 5'd20;
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factor[12] = 5'd24; factor[13] = 5'd24; factor[14] = 5'd30; factor[15] = 5'd30;
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end
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endmodule // jtopl_pg_sum
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