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61 lines
1.9 KiB
Verilog
61 lines
1.9 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 20-6-2020
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*/
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// Accumulates an arbitrary number of inputs with saturation
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// restart the sum when input "zero" is high
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module jtopl_single_acc #(parameter
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INW=13, // input data width
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OUTW=16 // output data width
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)(
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input clk,
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input cenop,
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input [INW-1:0] op_result,
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input sum_en,
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input zero,
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output reg [OUTW-1:0] snd
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);
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// for full resolution use INW=14, OUTW=16
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// for cut down resolution use INW=9, OUTW=12
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// OUTW-INW should be > 0
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reg signed [OUTW-1:0] next, acc, current;
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reg overflow;
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wire [OUTW-1:0] plus_inf = { 1'b0, {(OUTW-1){1'b1}} }; // maximum positive value
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wire [OUTW-1:0] minus_inf = { 1'b1, {(OUTW-1){1'b0}} }; // minimum negative value
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always @(*) begin
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current = sum_en ? { {(OUTW-INW){op_result[INW-1]}}, op_result } : {OUTW{1'b0}};
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next = zero ? current : current + acc;
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overflow = !zero &&
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(current[OUTW-1] == acc[OUTW-1]) &&
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(acc[OUTW-1]!=next[OUTW-1]);
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end
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always @(posedge clk) if( cenop ) begin
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acc <= overflow ? (acc[OUTW-1] ? minus_inf : plus_inf) : next;
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if(zero) snd <= acc;
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end
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endmodule |