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32 lines
723 B
Systemverilog
32 lines
723 B
Systemverilog
module aluShifter( input [31:0] data,
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input isByte, input isLong, swapWords,
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input dir, input cin,
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output logic [31:0] result);
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// output reg cout
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logic [31:0] tdata;
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// size mux, put cin in position if dir == right
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always_comb begin
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tdata = data;
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if( isByte & dir)
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tdata[8] = cin;
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else if( !isLong & dir)
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tdata[16] = cin;
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end
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always_comb begin
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// Reverse alu/alue position for MUL & DIV
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// Result reversed again
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if( swapWords & dir)
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result = { tdata[0], tdata[31:17], cin, tdata[15:1]};
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else if( swapWords)
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result = { tdata[30:16], cin, tdata[14:0], tdata[31]};
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else if( dir)
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result = { cin, tdata[31:1]};
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else
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result = { tdata[30:0], cin};
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end
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endmodule
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