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https://github.com/Gehstock/Mist_FPGA.git
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80 lines
3.1 KiB
Plaintext
80 lines
3.1 KiB
Plaintext
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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// INT3
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.at 0xcc;
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b_sel IMMEDIATE, immediate 0xc, alu_op SELB, tmp_wr_en, jmp do_int;
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// The same as above, but this time it's a 8 bit interrupt number.
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.at 0xcd;
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b_sel IMMEDIATE, alu_op SELB, mar_wr_sel Q, mar_write, jmp intN;
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.auto_address;
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intN:
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a_sel MAR, b_sel IMMEDIATE, immediate 0xff, alu_op AND, mar_write,
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mar_wr_sel Q;
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a_sel MAR, b_sel IMMEDIATE, immediate 0x4, alu_op MUL, tmp_wr_en,
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jmp do_int;
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// INTO: the same as int3, but conditional on OF being set.
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.at 0xce;
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alu_op GETFLAGS, mdr_write, jmp into;
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.auto_address;
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into:
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b_sel IMMEDIATE, immediate 0x10, alu_op SELB, tmp_wr_en,
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jmp_if_taken into_taken, ra_sel SP;
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next_instruction;
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into_taken:
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jmp do_int;
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// Process an interrupt.
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// TEMP: interrupt vector address
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//
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// This is a reasonably large microprocedure, but a reasonable amount of
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// repetition. Start by storing the flags + CS:IP to the stack, clear TF+IF
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// and then load the new CS:IP. As the vectors are stored in segment 0, this
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// requires temporarily setting CS to 0 to read the final vector address.
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.at 0x12d;
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do_int:
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alu_op GETFLAGS, mdr_write, ra_sel SP, jmp do_int_main;
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.auto_address;
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do_int_main:
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a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB,
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mar_write, mar_wr_sel Q, segment SS, segment_force;
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segment SS, segment_force, mem_write;
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a_sel MAR, b_sel IMMEDIATE, immediate 0x2, alu_op SUB,
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mar_write, mar_wr_sel Q, segment_force, segment CS;
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b_sel SR, alu_op SELB, mdr_write, segment SS, segment_force;
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segment SS, segment_force, mem_write;
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a_sel MAR, b_sel IMMEDIATE, immediate 0x2, alu_op SUB,
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mar_write, mar_wr_sel Q;
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a_sel IP, alu_op SELA, mdr_write, segment SS, segment_force;
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segment SS, segment_force, mem_write;
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a_sel MAR, alu_op SELA, rd_sel_source MICROCODE_RD_SEL,
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rd_sel SP;
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b_sel IMMEDIATE, immediate 0x0, alu_op SETFLAGSB, update_flags IF TF;
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b_sel IMMEDIATE, immediate 0x0, alu_op SELB, segment_force,
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segment CS, segment_wr_en;
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b_sel TEMP, alu_op SELB, mar_wr_sel Q, mar_write, segment CS,
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segment_force;
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segment_force, segment CS, mem_read;
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a_sel MDR, alu_op SELA, load_ip;
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a_sel MAR, b_sel IMMEDIATE, immediate 0x2, alu_op ADD, mar_write,
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mar_wr_sel Q, segment CS, segment_force;
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segment_force, segment CS, mem_read;
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a_sel MDR, alu_op SELA, segment_force, segment CS,
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segment_wr_en, next_instruction;
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