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https://github.com/Gehstock/Mist_FPGA.git
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60 lines
1.6 KiB
VHDL
60 lines
1.6 KiB
VHDL
-------------------------------------------------------------------------------
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-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity dpram is
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generic (
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addr_width_g : integer := 8;
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data_width_g : integer := 8
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);
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port (
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clk_a_i : in std_logic;
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we_i : in std_logic;
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addr_a_i : in std_logic_vector(addr_width_g-1 downto 0);
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data_a_i : in std_logic_vector(data_width_g-1 downto 0);
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data_a_o : out std_logic_vector(data_width_g-1 downto 0);
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clk_b_i : in std_logic;
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addr_b_i : in std_logic_vector(addr_width_g-1 downto 0);
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data_b_o : out std_logic_vector(data_width_g-1 downto 0)
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);
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end entity;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of dpram is
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type ram_t is array (natural range 2**addr_width_g-1 downto 0) of
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std_logic_vector(data_width_g-1 downto 0);
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signal ram_q : ram_t;
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begin
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mem_a: process (clk_a_i)
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variable read_addr_v : unsigned(addr_width_g-1 downto 0);
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begin
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if rising_edge(clk_a_i) then
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read_addr_v := unsigned(addr_a_i);
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if we_i = '1' then
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ram_q(to_integer(read_addr_v)) <= data_a_i;
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end if;
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data_a_o <= ram_q(to_integer(read_addr_v));
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end if;
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end process mem_a;
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mem_b: process (clk_b_i)
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variable read_addr_v : unsigned(addr_width_g-1 downto 0);
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begin
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if rising_edge(clk_b_i) then
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read_addr_v := unsigned(addr_b_i);
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data_b_o <= ram_q(to_integer(read_addr_v));
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end if;
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end process mem_b;
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end rtl;
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