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90 lines
2.9 KiB
VHDL
90 lines
2.9 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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--
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-- Generic single port RAM.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity spram is
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generic (
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addr_width_g : integer := 8;
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data_width_g : integer := 8
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);
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port (
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clk_i : in std_logic;
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we_i : in std_logic;
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addr_i : in std_logic_vector(addr_width_g-1 downto 0);
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data_i : in std_logic_vector(data_width_g-1 downto 0);
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data_o : out std_logic_vector(data_width_g-1 downto 0)
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);
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end spram;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of spram is
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type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
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signal ram_q : ram_t
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-- pragma translate_off
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:= (others => (others => '0'))
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-- pragma translate_on
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;
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signal read_addr_q : unsigned(addr_width_g-1 downto 0);
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begin
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process (clk_i)
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begin
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if rising_edge(clk_i) then
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if we_i = '1' then
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ram_q(to_integer(unsigned(addr_i))) <= data_i;
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end if;
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read_addr_q <= unsigned(addr_i);
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end if;
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end process;
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data_o <= ram_q(to_integer(read_addr_q));
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end rtl;
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