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87 lines
1.5 KiB
Verilog
87 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 19:38:32 05/01/2018
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// Design Name: LS245
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// Module Name: System86/LS245_tb.v
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// Project Name: Namco System86 simulation
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// Target Device:
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// Tool versions:
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// Description: LS245 - Octal Bus Transceiver - test bench
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//
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// Verilog Test Fixture created by ISE for module: LS245
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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////////////////////////////////////////////////////////////////////////////////
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module LS245_tb;
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// Inputs
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reg DIR;
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reg OE;
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// Bidirs
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wire [7:0] A;
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wire [7:0] B;
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reg [7:0] AIn = 'h99;
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reg [7:0] BIn = 'h66;
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assign A = DIR ? AIn : 8'bZ;
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assign B = ~DIR ? BIn : 8'bZ;
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// Instantiate the Unit Under Test (UUT)
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LS245 uut (
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.DIR(DIR),
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.OE(OE),
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.A(A),
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.B(B)
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);
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integer e;
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integer d;
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initial begin
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// Initialize Inputs
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DIR = 0;
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OE = 0;
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// Wait 100 ns for global reset to finish
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#100;
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// Add stimulus here
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$display("OE\tDIR\tAIn\tBIn\tAOut\tBOut");
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for (e = 0; e <= 1; e=e+1) begin
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OE <= e[0];
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for (d = 0; d <= 1; d=d+1) begin
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DIR <= d[0];
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#4
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$display("%s\t%s\t0x%x\t0x%x\t0x%x\t0x%x",
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OE ? "H" : "L",
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DIR ? "H" : "L",
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AIn,
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BIn,
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A,
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B);
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end
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end
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$finish;
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end
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endmodule
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