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Gehstock.Mist_FPGA/common/CPU/t48/p1-c.vhd
2020-05-13 15:54:31 +02:00

18 lines
387 B
VHDL

-------------------------------------------------------------------------------
--
-- The Port 1 unit.
-- Implements the Port 1 logic.
--
-- $Id: p1-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_p1_rtl_c0 of t48_p1 is
for rtl
end for;
end t48_p1_rtl_c0;