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Gehstock.Mist_FPGA/Computer_MiST/OricInFPGA_MiST/rtl/pll.qip
2019-07-22 00:02:14 +02:00

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]