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76 lines
2.3 KiB
Systemverilog
76 lines
2.3 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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// Multi-cycle-path formulation with feedback as described in "Clock Domain
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// Crossing (CDC) Design & Verification Techniques Using SystemVerilog" by
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// Clifford E. Cummings.
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`default_nettype none
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module MCP #(parameter width = 8,
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parameter reset_val = 8'b0)
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(input logic reset,
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input logic clk_a,
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output logic a_ready,
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input logic a_send,
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input logic [width-1:0] a_datain,
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input logic clk_b,
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output logic [width-1:0] b_data,
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output logic b_load);
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logic [width-1:0] tx_sample;
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assign a_ready = a_ack | ~tx_busy;
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reg a_en;
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wire a_ack;
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reg tx_busy;
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wire a_load = a_send & a_ready;
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wire b_ack;
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assign b_data = tx_sample;
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SyncPulse BLoadPulse(.clk(clk_b),
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.d(a_en),
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.p(b_load),
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.q(b_ack));
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SyncPulse AAckPulse(.clk(clk_a),
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.d(b_ack),
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.p(a_ack),
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// verilator lint_off PINCONNECTEMPTY
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.q()
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// verilator lint_on PINCONNECTEMPTY
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);
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always_ff @(posedge clk_a)
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a_en <= a_en ^ a_load;
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always_ff @(posedge clk_a or posedge reset) begin
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if (reset)
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tx_busy <= 1'b0;
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else begin
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if (a_ack)
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tx_busy <= 1'b0;
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if (a_send)
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tx_busy <= 1'b1;
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end
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end
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always_ff @(posedge clk_a or posedge reset)
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if (reset)
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tx_sample <= reset_val;
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else if (a_load)
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tx_sample <= a_datain;
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endmodule
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