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Gehstock.Mist_FPGA/Computer_MiST/Apple - 2_MiST/rtl/CLK28MPLL.qip
Gehstock b4920d3288 1
2018-10-27 14:54:23 +02:00

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "8.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "CLK28MPLL.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "CLK28MPLL.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "CLK28MPLL.ppf"]