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285 lines
8.5 KiB
VHDL
285 lines
8.5 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- The Timer/Counter unit.
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--
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-- $Id: timer.vhd,v 1.7 2006/11/30 14:31:59 arniml Exp $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t48_pack.word_t;
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use work.t48_pack.mstate_t;
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entity t48_timer is
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generic (
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-- state in which T1 is sampled (3 or 4)
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sample_t1_state_g : integer := 4
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);
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port (
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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t1_i : in std_logic;
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clk_mstate_i : in mstate_t;
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-- T48 Bus Interface ------------------------------------------------------
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data_i : in word_t;
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data_o : out word_t;
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read_timer_i : in boolean;
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write_timer_i : in boolean;
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-- Decoder Interface ------------------------------------------------------
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start_t_i : in boolean;
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start_cnt_i : in boolean;
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stop_tcnt_i : in boolean;
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overflow_o : out std_logic
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);
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end t48_timer;
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library ieee;
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use ieee.numeric_std.all;
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use work.t48_pack.all;
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architecture rtl of t48_timer is
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-- the 8 bit counter core
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signal counter_q : unsigned(word_t'range);
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signal overflow_q : boolean;
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-- increment signal for the counter core
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type inc_type_t is (NONE, TIMER, COUNTER);
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signal increment_s : boolean;
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signal inc_sel_q : inc_type_t;
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-- T1 edge detector
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signal t1_q : std_logic;
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signal t1_inc_s : boolean;
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-- timer prescaler
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signal prescaler_q : unsigned(4 downto 0);
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signal pre_inc_s : boolean;
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begin
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-----------------------------------------------------------------------------
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-- Verify the generics
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-----------------------------------------------------------------------------
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-- pragma translate_off
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assert (sample_t1_state_g = 3) or (sample_t1_state_g = 4)
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report "sample_t1_state_g must be either 3 or 4!"
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severity failure;
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-- pragma translate_on
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-----------------------------------------------------------------------------
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-- Process t1_edge
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--
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-- Purpose:
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-- Implements the edge detector for T1.
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--
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t1_edge: process (t1_i,
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t1_q,
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clk_mstate_i)
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begin
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t1_inc_s <= false;
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-- sample in state according to generic
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-- Old devices: sample at the beginning of state 3
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-- New devices: sample in state 4
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if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or
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(sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then
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-- detect falling edge
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if t1_q = '1' and t1_i = '0' then
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t1_inc_s <= true;
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end if;
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end if;
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end process t1_edge;
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--
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-----------------------------------------------------------------------------
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pre_inc_s <= clk_mstate_i = MSTATE4 and prescaler_q = 31;
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-----------------------------------------------------------------------------
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-- Process inc_sel
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--
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-- Purpose:
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-- Select increment source (timer, counter or none).
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--
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inc_sel: process (inc_sel_q,
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pre_inc_s,
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t1_inc_s)
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begin
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-- default assignment
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increment_s <= false;
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case inc_sel_q is
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when NONE =>
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increment_s <= false;
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when TIMER =>
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increment_s <= pre_inc_s;
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when COUNTER =>
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increment_s <= t1_inc_s;
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when others =>
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null;
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end case;
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end process inc_sel;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process regs
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--
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-- Purpose:
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-- Implements the counter, the prescaler and other registers.
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--
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regs: process (res_i, clk_i)
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begin
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if res_i = res_active_c then
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overflow_q <= false;
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t1_q <= '0';
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prescaler_q <= (others => '0');
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inc_sel_q <= NONE;
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counter_q <= (others => '0');
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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-- Counter Core and overflow ------------------------------------------
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overflow_q <= false;
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if write_timer_i then
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counter_q <= unsigned(data_i);
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elsif increment_s then
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counter_q <= counter_q + 1;
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if counter_q = 255 then
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overflow_q <= true;
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end if;
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end if;
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-- T1 edge detector ---------------------------------------------------
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if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or
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(sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then
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t1_q <= t1_i;
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end if;
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-- Prescaler ----------------------------------------------------------
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if start_t_i then
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prescaler_q <= (others => '0');
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elsif clk_mstate_i = MSTATE3 then
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prescaler_q <= prescaler_q + 1;
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end if;
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-- Increment Selector -------------------------------------------------
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if start_t_i then
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inc_sel_q <= TIMER;
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elsif start_cnt_i then
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inc_sel_q <= COUNTER;
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elsif stop_tcnt_i then
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inc_sel_q <= NONE;
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end if;
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end if;
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end if;
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end process regs;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output Mapping.
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-----------------------------------------------------------------------------
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data_o <= std_logic_vector(counter_q)
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when read_timer_i else
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(others => bus_idle_level_c);
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overflow_o <= to_stdLogic(overflow_q);
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end rtl;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: timer.vhd,v $
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-- Revision 1.7 2006/11/30 14:31:59 arniml
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-- reset counter_q
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--
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-- Revision 1.6 2005/06/11 10:08:43 arniml
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-- introduce prefix 't48_' for all packages, entities and configurations
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--
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-- Revision 1.5 2004/07/11 16:51:33 arniml
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-- cleanup copyright notice
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--
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-- Revision 1.4 2004/07/04 13:06:45 arniml
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-- counter_q is not cleared during reset
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-- this would match all different descriptions of the Counter as
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-- a) if the software assumes that the Counter is modified during reset, it
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-- will initialize the Counter anyhow
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-- b) the special case 'Counter not modified during reset' is covered
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--
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-- Revision 1.3 2004/05/16 15:32:57 arniml
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-- fix edge detector bug for counter
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--
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-- Revision 1.2 2004/04/15 22:05:13 arniml
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-- increment prescaler with MSTATE4
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--
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-- Revision 1.1 2004/03/23 21:31:53 arniml
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-- initial check-in
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--
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-------------------------------------------------------------------------------
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