mirror of
https://github.com/Gehstock/Mist_FPGA.git
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108 lines
2.2 KiB
Verilog
108 lines
2.2 KiB
Verilog
/****************************************************************************
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PIA 8255
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Version 050111
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Copyright(C) 2004,2005 Tatsuyuki Satoh
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This software is provided "AS IS", with NO WARRANTY.
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NON-COMMERCIAL USE ONLY
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Histry:
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2005. 1.11 Ver.0.1
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Note:
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Distributing all and a part is prohibited.
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Because this version is developer-alpha version.
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mode 0,1,2 handshake is not supported , mode 3 bit I/O only
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****************************************************************************/
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module PIA8255(
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I_RESET,
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I_A,
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I_CS,
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I_RD,
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I_WR,
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I_D,
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O_D,
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//
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I_PA,O_PA,
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//
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I_PB,O_PB,
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//
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I_PC,O_PC
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);
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input I_RESET;
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input [1:0] I_A;
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input I_CS;
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input I_WR;
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input I_RD;
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input [7:0] I_D;
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output [7:0] O_D;
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input [7:0] I_PA,I_PB,I_PC;
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output [7:0] O_PA,O_PB,O_PC;
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////////////////////////////////////////////////////////////////////////////
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reg [7:0] pa_o,pb_o,pc_o;
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reg pa_dir , pb_dir , pcl_dir , pch_dir;
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reg [1:0] pa_mode;
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reg pb_mode;
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// wirte data
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always @(negedge I_WR or posedge I_RESET)
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begin
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if(I_RESET) begin
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pa_o <= 8'h00;
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pb_o <= 8'h00;
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pc_o <= 8'h00;
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pa_mode <= 2'b00;
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pa_dir <= 1'b1;
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pcl_dir <= 1'b1;
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pb_mode <= 1'b0;
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pb_dir <= 1'b1;
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pch_dir <= 1'b1;
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end else if(I_CS) begin
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case(I_A)
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2'b00:pa_o <= I_D;
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2'b01:pb_o <= I_D;
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2'b10:pc_o <= I_D;
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2'b11:begin
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if(I_D[7])
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begin
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// mode set
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pa_mode <= I_D[6:5];
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pa_dir <= I_D[4];
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pch_dir <= I_D[3];
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pb_mode <= I_D[2];
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pb_dir <= I_D[1];
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pcl_dir <= I_D[0];
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end else begin
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// bit operation
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pc_o[I_D[3:1]] <= I_D[0];
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end
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end
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endcase
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end
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end
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// read data
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//wire read_gate = I_CS & I_RD;
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wire [7:0] pa_r = pa_dir ? I_PA : pa_o;
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wire [7:0] pb_r = pb_dir ? I_PB : pb_o;
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wire [7:0] pc_r = { pch_dir ? I_PC[7:4] : pc_o[7:4] , pcl_dir ? I_PC[3:0] : pc_o[3:0] };
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wire [7:0] ct_r = {1'b0,pa_mode,pa_dir,pcl_dir,pb_mode,pb_dir,pch_dir};
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assign O_D = (I_A==2'b00) ? pa_r :
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(I_A==2'b01) ? pb_r :
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(I_A==2'b10) ? pc_r :
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ct_r;
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// port output
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assign O_PA = pa_o;
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assign O_PB = pb_o;
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assign O_PC = pc_o;
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endmodule
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