mirror of
https://github.com/Gehstock/Mist_FPGA.git
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139 lines
3.6 KiB
VHDL
139 lines
3.6 KiB
VHDL
--
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-- i8253.vhd
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--
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-- Intel 8253 (PIT:Programmable Interval Timer) partiality compatible module
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-- for MZ-700 on FPGA
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--
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-- PIT main module
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--
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-- Nibbles Lab. 2005
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity i8253 is
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Port ( RST : in std_logic;
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CLK : in std_logic;
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A : in std_logic_vector(1 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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CS : in std_logic;
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WR : in std_logic;
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RD : in std_logic;
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CLK0 : in std_logic;
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GATE0 : in std_logic;
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OUT0 : out std_logic;
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CLK1 : in std_logic;
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GATE1 : in std_logic;
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OUT1 : out std_logic;
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CLK2 : in std_logic;
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GATE2 : in std_logic;
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OUT2 : out std_logic);
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end i8253;
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architecture Behavioral of i8253 is
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signal WRD0 : std_logic;
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signal WRD1 : std_logic;
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signal WRD2 : std_logic;
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signal WRM0 : std_logic;
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signal WRM1 : std_logic;
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signal WRM2 : std_logic;
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--signal RD0 : std_logic;
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signal RD1 : std_logic;
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signal RD2 : std_logic;
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signal DO0 : std_logic_vector(7 downto 0);
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signal DO1 : std_logic_vector(7 downto 0);
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signal DO2 : std_logic_vector(7 downto 0);
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component counter0
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Port ( DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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WRD : in std_logic;
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WRM : in std_logic;
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KCLK : in std_logic;
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CLK : in std_logic;
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GATE : in std_logic;
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POUT : out std_logic);
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end component;
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component counter1
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Port ( DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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WRD : in std_logic;
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WRM : in std_logic;
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KCLK : in std_logic;
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CLK : in std_logic;
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GATE : in std_logic;
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POUT : out std_logic);
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end component;
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component counter2
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Port ( DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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WRD : in std_logic;
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WRM : in std_logic;
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KCLK : in std_logic;
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RD : in std_logic;
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CLK : in std_logic;
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GATE : in std_logic;
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POUT : out std_logic);
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end component;
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begin
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WRD0<=WR when CS='0' and A="00" else '1';
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WRD1<=WR when CS='0' and A="01" else '1';
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WRD2<=WR when CS='0' and A="10" else '1';
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WRM0<=WR when CS='0' and A="11" and DI(7 downto 6)="00" else '1';
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WRM1<=WR when CS='0' and A="11" and DI(7 downto 6)="01" else '1';
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WRM2<=WR when CS='0' and A="11" and DI(7 downto 6)="10" else '1';
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-- RD0<=RD when CS='0' and A="00" else '1';
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RD1<=RD when CS='0' and A="01" else '1';
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RD2<=RD when CS='0' and A="10" else '1';
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DO<=DO0 when CS='0' and A="00" else
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DO1 when CS='0' and A="01" else
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DO2 when CS='0' and A="10" else (others=>'1');
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CTR0 : counter0 port map (
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DI => DI,
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DO => DO0,
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WRD => WRD0,
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WRM => WRM0,
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KCLK => CLK,
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CLK => CLK0,
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GATE => GATE0,
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POUT => OUT0);
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CTR1 : counter1 port map (
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DI => DI,
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DO => DO1,
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WRD => WRD1,
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WRM => WRM1,
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KCLK => CLK,
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CLK => CLK1,
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GATE => GATE1,
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POUT => OUT1);
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CTR2 : counter2 port map (
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DI => DI,
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DO => DO2,
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WRD => WRD2,
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WRM => WRM2,
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KCLK => CLK,
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RD => RD2,
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CLK => CLK2,
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GATE => GATE2,
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POUT => OUT2);
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end Behavioral;
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